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TransEDA Announces Simulation Edge Suite for Faster Design Verification At 50 Percent Savings
LOS GATOS, Calif.--(BUSINESS WIRE)--Aug. 20, 2001--
TransEDA®, the leader in ready-to-use verification solutions,
today announced its Simulation Edge(TM) verification suite, offering
FPGA, ASIC and SoC designers faster time-to-market at half the price,
with TransEDA's integrated design verification solutions.
The Simulation Edge suite is ready-to-use with existing simulation
environments and verification flows to dramatically speed the
functional verification process. The suite offers a configurable HDL
checker, coverage analysis, and test suite analysis in one bundle with
a common interface. At up to 50 percent off the regular list price for
the combined set of tools, designers can speed time-to-market while
keeping tool costs and vendor count to the absolute minimum.
``TransEDA's Simulation Edge suite is an integrated verification
solution at a great bundled price,'' said Tom Borgstrom, vice president
of marketing at TransEDA. ``The Simulation Edge suite can be used by
all RTL designers to achieve a time-to-market edge by reducing the
simulation iterations needed for functional closure. It is also
painless to install, integrate, learn and use so designers can get
up and running quickly. Add to this the time saved by working with a
single vendor for a variety of verification tools, and designers
really get an edge.''
Simulation Edge Suite - An Integrated, Ready-to-Use Solution
The Simulation Edge verification suite offers a powerful
combination of three best-in-class verification tools that work
seamlessly together and are easily integrated into existing RTL design
flows:
- VN-Check(TM) Configurable HDL Checker: With built-in rule sets
and easily configured rules, VN-Check identifies bugs before
simulation when it is easiest to fix them, cutting time and
effort spent on simulation.
- VN-Cover(TM) Coverage Analysis: The leading Verilog, VHDL and
dual-language coverage solution, VN-Cover enables designers to
identify and focus test development effort on the areas of a
design that have yet to be fully simulated, slashing the
number of simulation iterations required.
- VN-Optimize(TM) Test Suite Analysis: Working seamlessly with
VN-Cover coverage results, VN-Optimize analyzes test sets from
large regression suites and identifies the smallest set of
tests that will meet verification goals, dramatically reducing
the time and resource requirements for regression testing.
Verification Navigator(TM)
The tools in the Simulation Edge suite are part of TransEDA's
Verification Navigator integrated design verification environment.
Verification Navigator provides tools that enable IC designers to
manage the verification process and shorten verification time. In
addition to VN-Check, VN-Cover and VN-Optimize, Verification Navigator
includes VN-Control(TM) Application Specific Test Automation.
Verification Navigator supports all leading Verilog, VHDL and
dual-language simulators and is available on the Solaris, HPUX, AIX,
Linux, Windows NT, and Windows 2000 platforms.
Pricing and Availability
The Simulation Edge verification suite, featuring VN-Check,
VN-Cover, and VN-Optimize, is available now through December 31, 2001,
in Verilog, VHDL, language neutral, and dual language configurations.
Pricing starts at $30,000 for a perpetual license, a 50 percent
savings off list price for the combined tools. Subscription-based
pricing is also available. For more information on the Simulation Edge
suite, visit www.transeda.com/simulationedge.
About TransEDA
TransEDA PLC (symbol TRA on the London Stock Exchange) develops
and markets ready-to-use verification solutions for electronic
field-programmable gate array (FPGA), application-specific integrated
circuit (ASIC), and system-on-chip (SoC) designs. The company's
verification IP library includes models for advanced microprocessors
and bus interfaces.
TransEDA's design verification software performs
application-specific test automation, configurable HDL checking,
functional, finite state machine (FSM) and code coverage analysis, and
test suite analysis. TransEDA's tier-1 list of customers includes 18
of the world's top 20 semiconductor vendors.
For more information, visit www.transeda.com or contact TransEDA
at 985 University Avenue, Los Gatos, California 95032 U.S.A.,
telephone 408/335-1300, fax 408/335-1319, email info@transeda.com.
Note: TransEDA is a registered trademark and Verification
Navigator, VN-Check, VN-Cover, VN-Optimize, and Simulation Edge are
trademarks of TransEDA. All other trademarks are properties of their
respective holders.
Contact:
In North America, Asia, and Japan:
TransEDA
Tom Borgstrom, 408/335-1303
tom.borgstrom@transeda.com
or
Armstrong Kendall, Inc.
Jen Bernier, 408/975-9863
jen@akipr.com
or
In the U.K. and Europe:
PentaCom
Sharon Graves, +44 1242 525205
sharon.graves@btinternet.com
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